rcfg_debug |
0 |
enable_pll_reconfig |
1 |
enable_advanced_avmm_options |
0 |
rcfg_jtag_enable |
1 |
rcfg_separate_avmm_busy |
1 |
rcfg_enable_avmm_busy_port |
0 |
set_capability_reg_enable |
1 |
set_user_identifier |
0 |
set_csr_soft_logic_enable |
1 |
dbg_embedded_debug_enable |
1 |
dbg_capability_reg_enable |
1 |
dbg_user_identifier |
0 |
dbg_stat_soft_logic_enable |
1 |
dbg_ctrl_soft_logic_enable |
1 |
rcfg_file_prefix |
altera_xcvr_atx_pll_a10 |
rcfg_sv_file_enable |
1 |
rcfg_h_file_enable |
1 |
rcfg_txt_file_enable |
0 |
rcfg_mif_file_enable |
1 |
rcfg_multi_enable |
0 |
set_rcfg_emb_strm_enable |
0 |
rcfg_emb_strm_enable |
0 |
rcfg_reduced_files_enable |
0 |
rcfg_profile_cnt |
2 |
rcfg_profile_select |
1 |
rcfg_profile_data0 |
|
rcfg_profile_data1 |
|
rcfg_profile_data2 |
|
rcfg_profile_data3 |
|
rcfg_profile_data4 |
|
rcfg_profile_data5 |
|
rcfg_profile_data6 |
|
rcfg_profile_data7 |
|
rcfg_params |
rcfg_debug,enable_pll_reconfig,rcfg_jtag_enable,rcfg_separate_avmm_busy,rcfg_enable_avmm_busy_port,set_capability_reg_enable,set_user_identifier,set_csr_soft_logic_enable,enable_pld_atx_cal_busy_port,support_mode,prot_mode,bw_sel,refclk_cnt,refclk_index,primary_pll_buffer,enable_8G_path,enable_16G_path,enable_pcie_clk,enable_cascade_out,enable_hip_cal_done_port,set_hip_cal_en,set_output_clock_frequency,set_auto_reference_clock_frequency,set_manual_reference_clock_frequency,set_fref_clock_frequency,set_m_counter,set_ref_clk_div,set_l_counter,set_l_cascade_counter,set_l_cascade_predivider,set_k_counter,enable_mcgb,mcgb_div,enable_hfreq_clk,enable_mcgb_pcie_clksw,mcgb_aux_clkin_cnt,enable_bonding_clks,enable_fb_comp_bonding,pma_width,enable_pld_mcgb_cal_busy_port |
rcfg_param_labels |
rcfg_debug,Enable dynamic reconfiguration,Enable Altera Debug Master Endpoint,Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE,Enable avmm_busy port,Enable capability registers,Set user-defined IP identifier,Enable control and status registers,enable_pld_atx_cal_busy_port,Support mode,Protocol mode,Bandwidth,Number of PLL reference clocks,Selected reference clock source,Primary PLL clock output buffer,Enable PLL GX clock output port,Enable PLL GT clock output port,Enable PCIe clock output port,Enable cascade clock output port,Enable calibration status ports for HIP,Enable PCIe hard IP calibration,PLL output frequency,PLL integer reference clock frequency,PLL fractional reference clock frequency,PLL fractional reference clock frequency,Multiply factor (M-Counter),Divide factor (N-Counter),Divide factor (L-Counter),Divide factor (L-Cascade Counter),predivide factor (L-Cascade Predivider),Fractional multiply factor (K),Include Master Clock Generation Block,Clock division factor,Enable x6/xN non-bonded high-speed clock output port,Enable PCIe clock switch interface,Number of auxiliary MCGB clock input ports.,Enable bonding clock output ports,Enable feedback compensation bonding,PMA interface width,enable_pld_mcgb_cal_busy_port |
rcfg_param_vals0 |
|
rcfg_param_vals1 |
|
rcfg_param_vals2 |
|
rcfg_param_vals3 |
|
rcfg_param_vals4 |
|
rcfg_param_vals5 |
|
rcfg_param_vals6 |
|
rcfg_param_vals7 |
|
hssi_pma_lc_refclk_select_mux_powerdown_mode |
powerup |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch0_src |
scratch0_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch1_src |
scratch1_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch2_src |
scratch2_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch3_src |
scratch3_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch4_src |
scratch4_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_refclk_src |
src_lvpecl |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_iqclk_sel |
power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch0_src |
scratch0_power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch1_src |
scratch1_power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch2_src |
scratch2_power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch3_src |
scratch3_power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch4_src |
scratch4_power_down |
hssi_pma_lc_refclk_select_mux_refclk_select |
ref_iqclk0 |
hssi_pma_lc_refclk_select_mux_silicon_rev |
20nm4 |
hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping |
ref_iqclk0 |
hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping |
power_down |
hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping |
power_down |
hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping |
power_down |
hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping |
power_down |
hssi_refclk_divider_silicon_rev |
20nm4 |
hssi_refclk_divider_clk_divider |
div2_off |
hssi_refclk_divider_core_clk_lvpecl |
core_clk_lvpecl_off |
hssi_refclk_divider_enable_lvpecl |
lvpecl_enable |
hssi_refclk_divider_optimal |
true |
hssi_refclk_divider_powerdown_mode |
powerup |
hssi_refclk_divider_sel_pldclk |
iqclk_sel_lvpecl |
hssi_refclk_divider_sup_mode |
user_mode |
hssi_refclk_divider_term_tristate |
tristate_off |
hssi_refclk_divider_vcm_pup |
pup_off |
hssi_refclk_divider_clkbuf_sel |
high_vcm |
hssi_refclk_divider_iostandard |
lvpecl |
atx_pll_silicon_rev |
20nm4 |
atx_pll_is_cascaded_pll |
false |
atx_pll_cgb_div |
1 |
atx_pll_pma_width |
40 |
atx_pll_lc_atb |
atb_selectdisable |
atx_pll_cp_compensation_enable |
true |
atx_pll_cp_current_setting |
cp_current_setting22 |
atx_pll_cp_testmode |
cp_normal |
atx_pll_cp_lf_3rd_pole_freq |
lf_3rd_pole_setting0 |
atx_pll_lf_cbig_size |
lf_cbig_setting4 |
atx_pll_cp_lf_order |
lf_3rd_order |
atx_pll_lf_resistance |
lf_setting1 |
atx_pll_lf_ripplecap |
lf_ripple_cap_0 |
atx_pll_cal_status |
cal_in_progress |
atx_pll_bonding |
pll_bonding |
atx_pll_expected_lc_boost_voltage |
0 |
atx_pll_power_rail_et |
950 |
atx_pll_dprio_lc_vreg_boost_scratch |
0 |
atx_pll_dprio_lc_vreg1_boost_scratch |
0 |
atx_pll_dprio_clk_vreg_boost_scratch |
0 |
atx_pll_dprio_mcgb_vreg_boost_scratch |
0 |
atx_pll_dprio_vreg_boost_step_size |
0 |
atx_pll_dprio_vreg1_boost_step_size |
0 |
atx_pll_dprio_clk_vreg_boost_step_size |
0 |
atx_pll_dprio_mcgb_vreg_boost_step_size |
0 |
atx_pll_dprio_lc_vreg_boost_expected_voltage |
0 |
atx_pll_dprio_lc_vreg1_boost_expected_voltage |
0 |
atx_pll_dprio_clk_vreg_boost_expected_voltage |
0 |
atx_pll_dprio_mcgb_vreg_boost_expected_voltage |
0 |
atx_pll_clk_high_perf_voltage |
0 |
atx_pll_clk_mid_power_voltage |
0 |
atx_pll_clk_low_power_voltage |
0 |
atx_pll_tank_sel |
lctank2 |
atx_pll_tank_band |
lc_band6 |
atx_pll_tank_voltage_coarse |
vreg_setting_coarse0 |
atx_pll_tank_voltage_fine |
vreg_setting5 |
atx_pll_output_regulator_supply |
vreg1v_setting0 |
atx_pll_overrange_voltage |
over_setting0 |
atx_pll_underrange_voltage |
under_setting4 |
atx_pll_fb_select |
direct_fb |
atx_pll_d2a_voltage |
d2a_setting_4 |
atx_pll_dsm_mode |
dsm_mode_integer |
atx_pll_dsm_out_sel |
pll_dsm_disable |
atx_pll_dsm_ecn_bypass |
false |
atx_pll_dsm_ecn_test_en |
false |
atx_pll_dsm_fractional_division |
1 |
atx_pll_dsm_fractional_value_ready |
pll_k_ready |
atx_pll_enable_lc_calibration |
true |
atx_pll_enable_lc_vreg_calibration |
true |
atx_pll_iqclk_mux_sel |
iqtxrxclk0 |
atx_pll_vco_bypass_enable |
false |
atx_pll_l_counter |
2 |
atx_pll_l_counter_enable |
true |
atx_pll_cascadeclk_test |
cascadetest_off |
atx_pll_hclk_divide |
1 |
atx_pll_enable_hclk |
hclk_disabled |
atx_pll_m_counter |
50 |
atx_pll_ref_clk_div |
1 |
atx_pll_bandwidth_range_high |
0 hz |
atx_pll_bandwidth_range_low |
0 hz |
atx_pll_bw_sel |
low |
atx_pll_calibration_mode |
cal_off |
atx_pll_datarate |
12500000000 bps |
atx_pll_device_variant |
device1 |
atx_pll_f_max_pfd |
160000000 Hz |
atx_pll_f_max_ref |
800000000 Hz |
atx_pll_f_max_tank_0 |
8800000000 Hz |
atx_pll_f_max_tank_1 |
11400000000 Hz |
atx_pll_f_max_tank_2 |
14400000000 Hz |
atx_pll_f_max_vco |
14400000000 Hz |
atx_pll_f_max_x1 |
8700000000 Hz |
atx_pll_f_min_pfd |
61440000 Hz |
atx_pll_f_min_ref |
61440000 Hz |
atx_pll_f_min_tank_0 |
6500000000 Hz |
atx_pll_f_min_tank_1 |
8800000000 Hz |
atx_pll_f_min_tank_2 |
11400000000 Hz |
atx_pll_f_min_vco |
7200000000 Hz |
atx_pll_initial_settings |
true |
atx_pll_l_counter_scratch |
1 |
atx_pll_lc_mode |
lccmu_normal |
atx_pll_n_counter_scratch |
1 |
atx_pll_output_clock_frequency |
6250000000 Hz |
atx_pll_power_mode |
low_power |
atx_pll_powerdown_mode |
powerup |
atx_pll_prot_mode |
basic_tx |
atx_pll_reference_clock_frequency |
125000000 Hz |
atx_pll_side |
side_unknown |
atx_pll_pm_speed_grade |
e3 |
atx_pll_sup_mode |
user_mode |
atx_pll_top_or_bottom |
tb_unknown |
atx_pll_vccdreg_clk |
vreg_clk5 |
atx_pll_vccdreg_fb |
vreg_fb8 |
atx_pll_vccdreg_fw |
vreg_fw5 |
atx_pll_regulator_bypass |
reg_enable |
atx_pll_vco_freq |
12500000000 Hz |
atx_pll_f_max_vco_fractional |
0 hz |
atx_pll_f_max_pfd_fractional |
0 hz |
atx_pll_min_fractional_percentage |
0 |
atx_pll_max_fractional_percentage |
100 |
atx_pll_analog_mode |
user_custom |
atx_pll_is_otn |
false |
atx_pll_is_sdi |
false |
atx_pll_primary_use |
hssi_x1 |
atx_pll_fpll_refclk_selection |
select_vco_output |
atx_pll_lc_to_fpll_l_counter_scratch |
1 |
atx_pll_lc_to_fpll_l_counter |
lcounter_setting0 |
atx_pll_pfd_delay_compensation |
normal_delay |
atx_pll_xcpvco_xchgpmplf_cp_current_boost |
normal_setting |
atx_pll_f_max_lcnt_fpll_cascading |
1200000000 |
atx_pll_pfd_pulse_width |
pulse_width_setting0 |
atx_pll_enable_idle_atx_pll_support |
idle_none |
enable_advanced_options |
0 |
enable_hip_options |
0 |
enable_manual_configuration |
1 |
generate_docs |
1 |
generate_add_hdl_instance_example |
0 |
device_family |
ARRIA10 |
device |
10AS066K3F40E2SG |
base_device |
NIGHTFURY4 |
test_mode |
0 |
enable_pld_atx_cal_busy_port |
1 |
enable_debug_ports_parameters |
0 |
support_mode |
user_mode |
message_level |
error |
pma_speedgrade |
e3 |
device_revision |
20nm4 |
prot_mode |
Basic |
prot_mode_fnl |
basic_tx |
primary_use |
hssi_x1 |
bw_sel |
low |
refclk_cnt |
1 |
refclk_index |
0 |
silicon_rev |
false |
fb_select_fnl |
direct_fb |
primary_pll_buffer |
GX clock output buffer |
enable_8G_buffer_fnl |
true |
enable_16G_buffer_fnl |
false |
enable_8G_path |
1 |
enable_16G_path |
0 |
enable_pcie_clk |
0 |
enable_cascade_out |
0 |
enable_atx_to_fpll_cascade_out |
0 |
enable_hip_cal_done_port |
0 |
set_hip_cal_en |
0 |
hip_cal_en |
disable |
dsm_mode |
dsm_mode_integer |
set_output_clock_frequency |
6250.0 |
output_clock_datarate |
12500.0 |
output_clock_frequency |
6250.0 MHz |
vco_freq |
12500.0 MHz |
datarate |
12500.0 Mbps |
enable_fractional |
0 |
set_auto_reference_clock_frequency |
125.0 |
set_manual_reference_clock_frequency |
100.0 |
reference_clock_frequency_fnl |
125.000000 MHz |
set_fref_clock_frequency |
100.0 |
feedback_clock_frequency_fnl |
156.25 |
select_manual_config |
false |
m_counter |
50 |
effective_m_counter |
1 |
set_m_counter |
1 |
ref_clk_div |
1 |
set_ref_clk_div |
1 |
l_counter |
2 |
set_l_counter |
2 |
l_cascade_counter |
1 |
set_l_cascade_counter |
4 |
l_cascade_predivider |
1 |
set_l_cascade_predivider |
1 |
k_counter |
1 |
set_k_counter |
1 |
auto_list |
61.881188 {m 101 effective_m 101 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 62.500000 {m 100 effective_m 100 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 63.131313 {m 99 effective_m 99 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 63.775510 {m 98 effective_m 98 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 64.432990 {m 97 effective_m 97 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 65.104167 {m 96 effective_m 96 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 65.789474 {m 95 effective_m 95 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 66.489362 {m 94 effective_m 94 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 67.204301 {m 93 effective_m 93 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 67.934783 {m 92 effective_m 92 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 68.681319 {m 91 effective_m 91 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 69.444444 {m 90 effective_m 90 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 70.224719 {m 89 effective_m 89 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 71.022727 {m 88 effective_m 88 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 71.839080 {m 87 effective_m 87 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 72.674419 {m 86 effective_m 86 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 73.529412 {m 85 effective_m 85 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 74.404762 {m 84 effective_m 84 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 75.301205 {m 83 effective_m 83 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 76.219512 {m 82 effective_m 82 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 77.160494 {m 81 effective_m 81 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 78.125000 {m 80 effective_m 80 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 79.113924 {m 79 effective_m 79 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 80.128205 {m 78 effective_m 78 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 81.168831 {m 77 effective_m 77 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 82.236842 {m 76 effective_m 76 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 83.333333 {m 75 effective_m 75 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 84.459459 {m 74 effective_m 74 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 85.616438 {m 73 effective_m 73 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 86.805556 {m 72 effective_m 72 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 88.028169 {m 71 effective_m 71 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 89.285714 {m 70 effective_m 70 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 90.579710 {m 69 effective_m 69 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 91.911765 {m 68 effective_m 68 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 93.283582 {m 67 effective_m 67 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 94.696970 {m 66 effective_m 66 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 96.153846 {m 65 effective_m 65 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 97.656250 {m 64 effective_m 64 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 99.206349 {m 63 effective_m 63 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 100.806452 {m 62 effective_m 62 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 102.459016 {m 61 effective_m 61 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 104.166667 {m 60 effective_m 60 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 105.932203 {m 59 effective_m 59 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 107.758621 {m 58 effective_m 58 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 109.649123 {m 57 effective_m 57 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 111.607143 {m 56 effective_m 56 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 113.636364 {m 55 effective_m 55 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 115.740741 {m 54 effective_m 54 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 117.924528 {m 53 effective_m 53 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 120.192308 {m 52 effective_m 52 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 122.549020 {m 51 effective_m 51 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 123.762376 {m 101 effective_m 101 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 125.000000 {m 50 effective_m 50 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 126.262626 {m 99 effective_m 99 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 127.551020 {m 49 effective_m 49 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 128.865979 {m 97 effective_m 97 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 130.208333 {m 48 effective_m 48 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 131.578947 {m 95 effective_m 95 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 132.978723 {m 47 effective_m 47 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 134.408602 {m 93 effective_m 93 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 135.869565 {m 46 effective_m 46 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 137.362637 {m 91 effective_m 91 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 138.888889 {m 45 effective_m 45 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 140.449438 {m 89 effective_m 89 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 142.045455 {m 44 effective_m 44 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 143.678161 {m 87 effective_m 87 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 145.348837 {m 43 effective_m 43 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 147.058824 {m 85 effective_m 85 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 148.809524 {m 42 effective_m 42 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 150.602410 {m 83 effective_m 83 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 152.439024 {m 41 effective_m 41 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 154.320988 {m 81 effective_m 81 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 156.250000 {m 40 effective_m 40 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 158.227848 {m 79 effective_m 79 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 160.256410 {m 78 effective_m 78 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 162.337662 {m 77 effective_m 77 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 164.473684 {m 76 effective_m 76 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 166.666667 {m 75 effective_m 75 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 168.918919 {m 74 effective_m 74 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 171.232877 {m 73 effective_m 73 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 173.611111 {m 72 effective_m 72 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 176.056338 {m 71 effective_m 71 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 178.571429 {m 70 effective_m 70 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 181.159420 {m 69 effective_m 69 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 183.823529 {m 68 effective_m 68 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 186.567164 {m 67 effective_m 67 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 189.393939 {m 66 effective_m 66 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 192.307692 {m 65 effective_m 65 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 195.312500 {m 64 effective_m 64 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 198.412698 {m 63 effective_m 63 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 201.612903 {m 62 effective_m 62 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 204.918033 {m 61 effective_m 61 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 208.333333 {m 60 effective_m 60 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 211.864407 {m 59 effective_m 59 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 215.517241 {m 58 effective_m 58 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 219.298246 {m 57 effective_m 57 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 223.214286 {m 56 effective_m 56 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 227.272727 {m 55 effective_m 55 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 231.481481 {m 54 effective_m 54 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 235.849057 {m 53 effective_m 53 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 240.384615 {m 52 effective_m 52 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 245.098039 {m 51 effective_m 51 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 247.524752 {m 101 effective_m 101 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 250.000000 {m 50 effective_m 50 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 252.525253 {m 99 effective_m 99 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 255.102041 {m 49 effective_m 49 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 257.731959 {m 97 effective_m 97 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 260.416667 {m 48 effective_m 48 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 263.157895 {m 95 effective_m 95 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 265.957447 {m 47 effective_m 47 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 268.817204 {m 93 effective_m 93 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 271.739130 {m 46 effective_m 46 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 274.725275 {m 91 effective_m 91 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 277.777778 {m 45 effective_m 45 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 280.898876 {m 89 effective_m 89 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 284.090909 {m 44 effective_m 44 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 287.356322 {m 87 effective_m 87 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 290.697674 {m 43 effective_m 43 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 294.117647 {m 85 effective_m 85 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 297.619048 {m 42 effective_m 42 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 301.204819 {m 83 effective_m 83 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 304.878049 {m 41 effective_m 41 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 308.641975 {m 81 effective_m 81 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 312.500000 {m 40 effective_m 40 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 316.455696 {m 79 effective_m 79 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 320.512821 {m 78 effective_m 78 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 324.675325 {m 77 effective_m 77 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 328.947368 {m 76 effective_m 76 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 333.333333 {m 75 effective_m 75 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 337.837838 {m 74 effective_m 74 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 342.465753 {m 73 effective_m 73 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 347.222222 {m 72 effective_m 72 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 352.112676 {m 71 effective_m 71 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 357.142857 {m 70 effective_m 70 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 362.318841 {m 69 effective_m 69 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 367.647059 {m 68 effective_m 68 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 373.134328 {m 67 effective_m 67 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 378.787879 {m 66 effective_m 66 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 384.615385 {m 65 effective_m 65 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 390.625000 {m 64 effective_m 64 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 396.825397 {m 63 effective_m 63 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 403.225806 {m 62 effective_m 62 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 409.836066 {m 61 effective_m 61 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 416.666667 {m 60 effective_m 60 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 423.728814 {m 59 effective_m 59 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 431.034483 {m 58 effective_m 58 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 438.596491 {m 57 effective_m 57 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 446.428571 {m 56 effective_m 56 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 454.545455 {m 55 effective_m 55 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 462.962963 {m 54 effective_m 54 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 471.698113 {m 53 effective_m 53 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 480.769231 {m 52 effective_m 52 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 490.196078 {m 51 effective_m 51 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 495.049505 {m 101 effective_m 101 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 500.000000 {m 50 effective_m 50 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 505.050505 {m 99 effective_m 99 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 510.204082 {m 49 effective_m 49 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 515.463918 {m 97 effective_m 97 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 520.833333 {m 48 effective_m 48 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 526.315789 {m 95 effective_m 95 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 531.914894 {m 47 effective_m 47 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 537.634409 {m 93 effective_m 93 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 543.478261 {m 46 effective_m 46 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 549.450549 {m 91 effective_m 91 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 555.555556 {m 45 effective_m 45 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 561.797753 {m 89 effective_m 89 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 568.181818 {m 44 effective_m 44 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 574.712644 {m 87 effective_m 87 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 581.395349 {m 43 effective_m 43 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 588.235294 {m 85 effective_m 85 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 595.238095 {m 42 effective_m 42 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 602.409639 {m 83 effective_m 83 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 609.756098 {m 41 effective_m 41 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 617.283951 {m 81 effective_m 81 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 625.000000 {m 40 effective_m 40 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 632.911392 {m 79 effective_m 79 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 641.025641 {m 78 effective_m 78 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 649.350649 {m 77 effective_m 77 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 657.894737 {m 76 effective_m 76 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 666.666667 {m 75 effective_m 75 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 675.675676 {m 74 effective_m 74 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 684.931507 {m 73 effective_m 73 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 694.444444 {m 72 effective_m 72 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 704.225352 {m 71 effective_m 71 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 714.285714 {m 70 effective_m 70 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 724.637681 {m 69 effective_m 69 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 735.294118 {m 68 effective_m 68 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 746.268657 {m 67 effective_m 67 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 757.575758 {m 66 effective_m 66 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 769.230769 {m 65 effective_m 65 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 781.250000 {m 64 effective_m 64 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 793.650794 {m 63 effective_m 63 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} |
manual_list |
|
pll_setting |
refclk {125.000000 MHz} m_cnt 50 n_cnt 1 l_cnt 2 k_cnt 1 l_cascade 1 l_cascade_predivider 1 outclk {6250.0 MHz} |
enable_fb_comp_bonding_fnl |
0 |
check_output_ports_pll |
0 |
iqclk_mux_sel |
iqtxrxclk0 |
set_altera_xcvr_atx_pll_a10_calibration_en |
1 |
calibration_en |
enable |
enable_analog_resets |
0 |
enable_ext_lockdetect_ports |
0 |
atx_pll_bonding_mode |
cpri_bonding |
lc_refclk_select |
0 |
enable_mcgb |
1 |
mcgb_div |
1 |
mcgb_div_fnl |
1 |
enable_hfreq_clk |
1 |
enable_mcgb_pcie_clksw |
0 |
mcgb_aux_clkin_cnt |
0 |
mcgb_in_clk_freq |
6250.0 |
mcgb_out_datarate |
12500.0 |
enable_bonding_clks |
0 |
enable_fb_comp_bonding |
0 |
mcgb_enable_iqtxrxclk |
disable_iqtxrxclk |
pma_width |
40 |
enable_mcgb_debug_ports_parameters |
0 |
enable_pld_mcgb_cal_busy_port |
0 |
check_output_ports_mcgb |
0 |
is_protocol_PCIe |
0 |
mapped_output_clock_frequency |
6250.0 MHz |
mapped_primary_pll_buffer |
GX clock output buffer |
mapped_hip_cal_done_port |
0 |
hssi_pma_cgb_master_prot_mode |
basic_tx |
hssi_pma_cgb_master_silicon_rev |
20nm4 |
hssi_pma_cgb_master_x1_div_m_sel |
divbypass |
hssi_pma_cgb_master_cgb_enable_iqtxrxclk |
disable_iqtxrxclk |
hssi_pma_cgb_master_ser_mode |
forty_bit |
hssi_pma_cgb_master_datarate |
12500000000 bps |
hssi_pma_cgb_master_cgb_power_down |
normal_cgb |
hssi_pma_cgb_master_observe_cgb_clocks |
observe_nothing |
hssi_pma_cgb_master_op_mode |
enabled |
hssi_pma_cgb_master_tx_ucontrol_reset_pcie |
pcscorehip_controls_mcgb |
hssi_pma_cgb_master_vccdreg_output |
vccdreg_nominal |
hssi_pma_cgb_master_input_select |
lcpll_top |
hssi_pma_cgb_master_input_select_gen3 |
unused |
gui_parameter_list |
K counter (valid in fractional mode),L counter (valid in non-cascade mode),M counter,N counter,L cascade predivider/VCO divider(valid in cascade mode) ,L cascade counter (valid in cascade mode),PLL output frequency,vco_freq,datarate |
gui_parameter_values |
1,2,50,1,select_vco_output,1,6250.0 MHz,12500.0 MHz,12500.0 Mbps |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |